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When TP3 not pulled low at rising edge Rising Edge of PWROK. XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 PCIE Port Config1 bit1, pulled low. Resistor Type/ValuePULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20KThe pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller.
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SIGNALCL_CLK CL_DATA CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN HDA_SDOUT HDA_SYNC GLAN_DOCK# ICH9 Integrated pull-up and pull-down ResistorsICH79 Rev.1.5Ĭantiga chipset and ICH9M I/O controller Hub strapping configurationMontevina Platform Design guide 22339 Rev.0.5Pin NameCFG ICH9M Functional Strap DefinitionsSignalHDA_SDOUT Thermal/Audio Block DiagramAlba DiscreteSheetE Title Size Document Number Custom Date:A B C D Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PORT_C_L AUD_INT_MIC_R PORT_C_R VREFOUT_C AUD_VREFOUT_C 4K7R2J-2-GP Thermal EMC2102DP2 VGA_THERMDA SC470P50V3JN-2GP DN2 VGA_THERMDC DMINUS DPLUSĬodec 92HD81HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_BĬPU_THERMDA MMBT3904-3-GP SC470P50V3JN-2GP SC1U10V3KX-3GP AUD_INT_MIC_L INT_MIC_L_R Title Size C Date: Document NumberĠR3-0-U-GP SPKR_PORT_D_L+ SPKR_PORT_D_LSPKR_PORT_D_RSPKR_PORT_D_R+ AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1 0R3-0-U-V-GP AUD_SPK_L1_R AUD_SPK_L2_R AUD_SPK_R2_R AUD_SPK_R1_R Title Size Document Number Custom5 4 3 2Įxpress CardSMB_CLK ICH_SMBCLK ICH_SMBDATA
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Wistron Corporation28,44Title Size Document Number Custom Date: 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.Ĭharger MAX8731A+VCC_CORE +1.05V_VCCP +VCC_GFX_CORE ICH9-MUSB 2.0/1.1 ports (12) PCI Express ports (6) High Definition Audio SATA ports (4) LPC I/F ACPI 1.1 USB 2.0ĬAMERA (Option) BluetoothRight Side: USB x 1ĭigital Mic Array 47 (Option) Internal Mic MIC IN HP OUT(On Express Card board)44 SYSTEM DC/DCTPS51117INPUTS OUTPUTS+VCC_GFX_CORE 39 SYSTEM DC/DCTPS51117INPUTS OUTPUTS+1.8V_SUS 38ĬardReader(7 in 1)SD/MMC MS/MS Pro/xD(On Express Card board)B
INTEL SM BUS CONTROLLER FOR DELL INSPIRON 15 5558 CODE
Project code Part Number PCB P/N Revision Top GND Signal Signal VCC Signal GND BottomRGB CRT Title Size Document Number Custom Date:5 4 3 2 Alba Discrete ATI M92-LP gDDR2 Schematics uFCPGA Mobile Penryn Intel Cantiga-PM + ICH9MC CĭY : Nopop Component GM : Pop when Cantiga is GM PM : Pop when Cantiga is PM G/P : BOM control if Cantiga is PM